Present high speed computer systems and particularly those of the next generation, require both subnanosecond high density integrated circuits and the packaging technology to fully exploit their capabilities.
Such packaging technology includes the acceptance of a family of integrated circuit packages, functionally arranged in comparatively large basic elements of partitioning. This insures that only minimum and regular interconnections are required at this level. Efficient cooling means are required to provide higher power densities in order to maximize the MSI and LSI. Interconnection schemes for the packages must be provided to secure impedance control, with elimination or reduction of cross talk problems created by fast rise times. Also, such control is necessary to account for signal propagation delays resulting from delays in the semiconductors themselves.
Underlying all of the foregoing is the need for a heretofore unavailable standard packaging technique for computer systems which is oriented toward high quantity production and assembly processes to achieve minimum costs. It is to these goals that the present invention is directed.